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  TLE7183F data sheet, v2.1, april 2008 automotive power
data sheet 2 v2.1, 2008-04-30 TLE7183F table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 pin assignment TLE7183F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 default state of inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 mosfet driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.1 output stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.2 operation at vs<12v - integrated charge pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.3 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 protection and diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.1 short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 overcurrent warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.3 dead time and shoot through protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.4 undervoltage shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.5 overvoltage shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.6 overtemperature warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.7 err pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 shunt signal conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 phase voltage feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 layout guide lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table of contents
vqfn-48-14 data sheet 3 v2.1, 2008-04-30 TLE7183F type options package marking TLE7183F scd1 vqfn-48-14 tle7183scd1 TLE7183F scd2 vqfn-48-14 tle7183scd2 TLE7183F scd3 vqfn-48-14 tle7183scd3 TLE7183F scd4 vqfn-48-14 tle7183scd4 TLE7183F scd5 vqfn-48-14 tle7183scd5 1 overview features ? compatible to very low ohmic normal level input n-channel mosfets ? separate input for each mosfet ? pwm frequency up to 30khz ? fulfils specification down to 5.5v supply voltage ? low emc sensitivity and emission ? vqfn-48 package with exposed heat slug ? control inputs with ttl characteristics ? separate source connection for each mosfet ? integrated minimum dead time ? shoot through protection ? short circuit protection with 5 fixed detection level available ? disable function and sleep mode ? detailed diagnosis ? thermal overload warning for driver ic ? integrated overcurrent warning ? integrated current sense amplifier ? 0 to 100% duty cycle ? green product (rohs compliant) ?aec qualified description the TLE7183F is a driver ic dedicated to control the 6 to 12 external mosfets forming the converter for high current 3 phase motor drives in the automotive sector. it incorporates features like short circuit detection, diagnosis and high output performance and combines it with typical automotive specific requirements like full functionality even at low battery voltages. its 3 high side and 3 low side output stages are powerful enough to drive mosfets with 400nc gate charge with approx. 150 ns fall and rise times. the TLE7183F can be ordered with 5 different options for a fixed short circuit detection level. please see table 2 for detailed information. typical applications are cooling fan, water pump, electro-hydraulic and electric power steering. the TLE7183F is designed for 12 vpower net.
TLE7183F block diagram data sheet 4 v2.1, 2008-04-30 2 block diagram figure 1 block diagram vs err1 ena1 vdh isp isn vthoc sh1 gh1 sl1 gl1 sh2 gh2 sl2 gl2 sh3 gh3 sl3 gl3 cl1 charge pump 1 under voltage det. ch1 cb1 cl2 charge pump 2 under voltage det. ch2 cb2 floating hs driver short circuit detection floating ls driver short circuit detection floating hs driver short circuit detection floating ls driver short circuit detection floating hs driver short circuit detection floating ls driver short circuit detection l e v e l s h i f t e r diagnostic logic under voltage over voltage overtemperature short circuit reset over current inh err1 gnd current sense opamp bias reference buffer over current warning vri vro vo phase voltage feed back u_fb v_fb w_fb agnd il1 ih1 il2 ih2 il3 ih3 input control shoot through protection dead time gnd dt ena2 tp
data sheet 5 v2.1, 2008-04-30 TLE7183F pin configuration 3 pin configuration 3.1 pin assignment TLE7183F figure 2 pin configuration 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 sl 3 gh3 sh 3 gnd gh2 sh 2 gl2 sl2 gnd cb2 gh1 sh 1 ena1 ih3 il3 ih2 gnd il2 ih1 il1 w_fb v_ fb u_fb gl3 ena2 agnd vo isn isp vr o vri gnd vth oc dt inh tle 7183 f topview ch2 cl2 ch1 cl1 cb1 gnd vs vd h er r1 err2 sl 1 gl1 tp
TLE7183F pin configuration data sheet 6 v2.1, 2008-04-30 3.2 pin definitions and functions pin symbol function 1 sl3 connection to source low side switch 3 2 gnd logic and power ground 3 vo output of opamp for shunt signal amplification 4 isn - input of opamp for shunt signal amplification 5 isp + input of opamp for shunt signal amplification 6 vri input of bias reference amplifier 7 vro output of bias reference amplifier 8 agnd analog ground especially for the current sense opamp 9 vthoc threshold voltage for overcurrent detection 10 tp test pin, connect to gnd of driver ic 11 dt dead time program pin 12 inh inhibit pin (active low) 13 il3 input for low side switch 3 (active high) 14 ih3 input for high side switch 3 (active low) 15 u_fb digital logic representation of the voltage phase u; positive logic 16 v_fb digital logic representation of the voltage phase v; positive logic 17 w_fb digital logic representation of the voltage phase w; positive logic 18 ena1 enable pin (active high) 19 ena2 enable pin (active high) 20 gnd logic and power ground 21 il1 input for low side switch 1 (active high) 22 ih1 input for high side switch 1 (active low) 23 il2 input for low side switch 2 (active high) 24 ih2 input for high side switch 2 (active low) 25 err1 error signal 1 26 err2 error signal 2 27 ch2 + terminal for pump capacitor of charge pump 2 28 ch1 + terminal for pump capacitor of charge pump 1 29 cl1 - terminal for pump capacitor of charge pump 1 30 vs voltage supply 31 cl2 - terminal for pump capacitor of charge pump 2 32 gnd logic and power ground 33 cb1 buffer capacitor for charge pump 1 34 vdh connection to drain of high side switches for short circuit detection 35 gl1 output to gate low side switch 1 36 sl1 connection to source low side switch 1 37 gnd logic and power ground 38 sh1 connection to source high side switch 1 39 gh1 output to gate high side switch 1 40 cb2 buffer capacitor for charge pump 2
data sheet 7 v2.1, 2008-04-30 TLE7183F pin configuration 41 gl2 output to gate low side switch 2 42 sl2 connection to source low side switch 2 43 gh2 output to gate high side switch 2 44 sh2 connection to source high side switch 2 45 gh3 output to gate high side switch 3 46 sh3 connection to source high side switch 3 47 gnd logic and power ground 48 gl3 output to gate low side switch 3 pin symbol function
TLE7183F general product characteristics data sheet 8 v2.1, 2008-04-30 4 general product characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) 40 c t j 150 c ; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 supply voltage v s -4.0 45 v with 10ohm and 1f 4.1.2 supply voltage v s -0.3 45 v ? 4.1.3 supply voltage v s -0.3 47 v t p <200ms 4.1.4 voltage range at ihx,ilx,errx, vo, dt, vthoc, enax, vri, vro v dp -0.3 6.0 v ? 4.1.5 voltage range at inh v inh -0.3 18.0 v ? 4.1.6 voltage range at tp v tp -0.3 2 v 4.1.7 voltage range at slx v sl -7 7 v ? 4.1.8 voltage range at shx v sh -7 45 v ? 4.1.9 voltage range at glx v gl -7 18 v ? 4.1.10 voltage range at ghx v gh -7 55 v ? 4.1.11 voltage difference gxx-sxx v gs -0.3 15 v ? 4.1.12 voltage range at vdh v vdh -0.3 55 v inh=high 4.1.13 voltage range at vdh v vdh -4.0 55 v inh=high; with r vdh >70 ? ; 200ms, 5x 4.1.14 voltage range at vdh v vdh -0.3 28 v inh=low 4.1.15 voltage range at vdh v vdh -4.0 28 v inh=low; with r vdh >70 ? ; 200ms, 5x 4.1.16 voltage range at cl1 v cl1 -0.3 25 v ? 4.1.17 voltage range at ch1, cb1 v ch1 -0.3 25 v ? 4.1.18 voltage difference ch1-cl1 v dc1 -0.3 25 v ? 4.1.19 voltage range at cl2 v cl2 -0.3 25 v ? 4.1.20 voltage range at ch2, cb2 v ch2 -0.3 45 v ? 4.1.21 voltage difference ch2-cl2 v cp2 -0.3 25 v ? 4.1.22 voltage range at isp, isn v isi -5 5 v ? 4.1.23 output current range at vo i vo -20 20 ma ? 4.1.24 gate resistor r gate 2? ? ? temperatures 4.1.25 junction temperature t j -40 150 c? 4.1.26 storage temperature t stg -55 150 c? 4.1.27 lead soldering temperature (1/16?? from body) t sol ?260 c?
data sheet 9 v2.1, 2008-04-30 TLE7183F general product characteristics attention: stresses above the ones listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for ex tended periods may af fect device reliability. attention: integrated protection functions are desi gned to prevent ic destruct ion under faul t conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.2 functional range 4.1.28 peak reflow soldering temperature 2) t ref ?260 c? thermal resistance 4.1.29 junction to case r thjc ?5k/w? power dissipation 4.1.30 power dissipation (dc) @ tcase=125c p tot ?2w? esd susceptibility 4.1.31 esd resistivity 3) v esd ?2kv 4.1.32 esd resistivity (charge device model) 4) v esd ?750v 1) not subject to production test, specified by design. 2) reflow profile ipc/jedec j-std-020c 3) esd susceptibility hbm according to eia/jesd 22-a 114b 4) esd susceptibility cdm according to eia/jesd 22-c 101 pos. parameter symbol limit values unit conditions min. max. 4.2.1 supply voltage 1)2) v s 5.5 5.5 20 28 vdc t<1s 4.2.2 duty cycle 3) d 0 100 % ? 4.2.3 pwm frequency f pwm 0 25 khz total gate charge 400nc 4.2.4 quiescent current 4) i q ?30av s ,v dh <20 v 4.2.5 quiescent current into vdh i q_vdh ?30av dh <20v; v s pin open 4.2.6 supply current at vs i vs ? ? 175 175 110 110 ma f pwm =25khz q g =250nc: v s = 5.5v v s = 14v v s = 17v v s = 20v 4.2.7 supply current at vs(device disabled by ena) i vs(o) ?60 50 ma vs=5.5v..17v vs=17v..20v 4.2.8 currrent into vdh (device not in sleep mode) i vdh 1.5 ma v vdh =5.5..20v inh=high absolute maximum ratings (cont?d) 1) 40 c t j 150 c ; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max.
TLE7183F general product characteristics data sheet 10 v2.1, 2008-04-30 note: within the functional range the ic operates as described in the circuit description. the electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 default state of inputs table 1 default state of inputs note: the load condition ?c=22nf; r load =1 ? ? in the paragraph ?electrical characteristics / dynamic charactersitic? means that r load is connected between the output gxx and the positive terminal of the c. the negative terminal of the c is connected to gnd and the corresponding sxx. the voltage is measured at the positive terminal of the c. 4.2.9 voltage difference cb2-vdh v cb2 -0.3 25 v operation mode 4.2.10 junction temperature t j -40 150 c 1) max ratings for tj has to be considered as well 2) for proper start up minimum vs=6.5v is required 3) duty cycle is referred to the high side input command (ihx); the duty cycles can be driven continuously and fully operational 4) total current consumption from power net (vs and vdh) pos. parameter symbol limit values unit conditions min. max. characteristic state remark default state of ilx (if ilx left open) low low side mosfets off default state of ihx (if ihx left open) high high side mosfets off default state of ena (if ena1 left open) low device outputs disabled default state of ena (if ena2 left open) low device outputs disabled default state of inh (if inh left open) low sleep mode, i q < 30 a default state of sense amplifier output v o (isp=isn=0v) zero ampere equivalent ? status of the device and the outputs when ena1=ena2=inh='1' device active and outputs functional vs=5.5..28v pull up or pull down integrated resistors ixx, ena 30k ? +/-40% ? pull down integrated resistor inh 45k ? +/-40% ?
data sheet 11 v2.1, 2008-04-30 TLE7183F description and electrical characteristics 5 description and electrical characteristics 5.1 mosfet driver 5.1.1 output stages the 3 low side and 3 high side powerful push-pull output stages of the TLE7183F are all floating blocks, each with its own source pin. this allows the direct connection of the output stage to the source of each single mosfet, allowing a perfect control of each gate-source voltage even when 200a are driven in the bridge with rise and fall times clearly below 1s. all 6 output stages have the same output power and thanks to the used charge pump principle they can be switched all up to 30khz. its output stages are powerful enough to drive mosfets with 400nc gate charge with approx. 150ns fall and rise times or even to run 12 mosfets with 200nc each with fall and rise times of approx. 150ns. maximum allowed power dissipation, max. junction temperature and the limited current capabilities of the charge pump limit the use for higher frequencies. each output stage has its own short circuit detection block. for more details about short circuit detection see chapter 5.2.1 . figure 3 block diagram of driver stages including short circuit detection
TLE7183F description and electrical characteristics data sheet 12 v2.1, 2008-04-30 5.1.2 operation at vs<12v - integrated charge pumps the TLE7183F provides a feature tailored to the requirements in 12v automotive applications. often the operation of an application has to be assured even at 9v supply voltage or lower. normally bridge driver ics provide in such conditions clearly less than 9v to the gate of the external mosfets, increasing their r dson and the associated power dissipation. the TLE7183F has two charge pump circuitries for external capacitors. the operation of the charge pumps is independent upon the pulse pattern of the mosfets. the output of the charge pumps are regulated. the first charge pump doubles the supply voltage as long as it is below 8v. at 8v supply voltage and above, charge pump 1 regulates its output to 15v typically. above 15v supply voltage, the output voltage of charge pump 1 will increase linearly.yet, the output will not exceed 25v. charge pump 2 is regulated as well but it is pumped to the voltage on vs. normally vdh and vs are in the same voltage range. the driver is not designed to have significant higher voltages at vdh compared to vs. this would lead to reduced supply voltages for the high side output stages. charge pump 1 supplies the low side mosfets and output stages for the low side mosfets with sufficient voltage to assure 10v at the mosfets gate even if the supply voltage is below 10v. charge pump 2 supplies the output stages for the high side mosfets with sufficient voltage to assure 10v at the mosfets gate. in addition, the charge pump 1 supplies most of the internal circuits of the driver ic, including charge pump 2. output of charge pump 1 is the buffer capacitor cb1 which is referenced to gnd. charge pump 2 supplies the high side mosfets and the output stages for the high side mosfets with sufficient voltage to assure 10v at the high side mosfet gate. output of charge pump 2 is buffer capacitor cb2 which is referenced to vdh. this concept allows to drive all external mosfets in the complete duty cycle range of 0 to 100% without taking care about recharging of any bootstrap capacitors. this simplifies the use in all applications especially in motor drives with block wise commutation. the charge pumps are only deactivated when the device is put into sleep mode via inh. during start up of the device it is not allowed to have any pwm patterns at the ilx and ihx pins until the charge pumps have ramped up to their final values or it is recommended to keep one enax pin low. so for proper wake up at v vswu the output stages of the driver ic have to be switched off or one enax pin has to kept low. the size of the charge pump capacitors (pump capacitors cpx as well as buffer capacitors cbx) can be varied between 1 f and 4.7 f. yet, larger capacitor values result in higher charge pump voltages and less voltage ripple on the charge pump buffer capacistors cbx (which supply the internal circuits as well as the external mosfets, pls. see above). besides the capacitance values the esr of the buffer capacitors cbx determines the voltage ripple as well. it is recommended to use buffer capacitors cbx that have small esr. pls. see also chapter 5.1.3 for capacitor selection. 5.1.3 sleep mode when the inh pin is set to low, the driver will be set to sleep mode. the inh pin switches off the complete supply structure of the device and leads finally to an undervoltage shut down of the complete driver. enabling the device with the inh pin means to switch on the supply structure. the device will run through power on reset during wake up. it is recommended to perform a reset by ena after wake up to remove possible err signals; reset is performed by keeping one or more ena pins low until the charge pump voltages have ramped up. enabling and disabling with the inh pin is not very fast. for fast enable / disable the ena pin is recommended. when the tle 7183 f is in inh mode (inh is low) or when the supply voltage is not available on the vs pin, then the driver ic is not supplied, the charge pumps are inactive and the charge pump capacitors are discharged. pin cb2 (+ terminal of buffer capacitor 2) will decay to gnd. when the battery voltage is still applied to vdh (- terminal of buffer capacitor 2) the buffer capacitor 2 will slowly charged to battery voltage, yet with reversed polarity compared to the polarity during regular operation. hence, it is important to use a buffer capacitor 2 (cb2) that can
data sheet 13 v2.1, 2008-04-30 TLE7183F description and electrical characteristics withstand both, +25 v during operation mode and -v bat during inh mode, e.g. a ceramic capacitor. in case of load dump during inh mode, the negative voltage across cb2 will be clamped to -31 v (cb2 referenced to vdh). 5.1.4 electrical characteristics electrical characteristics mosfet drivers - dc characteristics v s = 5.5 to 20v, t j = -40 to +150 c, f pwm < 25khz , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.1.1 low level output voltage v g_ll ??0.2vi=30ma 5.1.2 high level output voltage, low side v g_hl 7.5 ? 13 v i=-2ma; vs=5.5..8v 5.1.3 high level output voltage, high side v g_hl 6.5 ? 13 v i=-2ma; vs=5.5..8v 5.1.4 high level output voltage v g_hl 9 ? 13 v i=-2ma; vs=8..20v 5.1.5 high level output voltage difference dv g_h ? ? 1.0 v i=-100ma; vs=20v 5.1.6 gate drive output voltage (device disabled via enax) v g(dis) ? ? 0.2 v disabled; vs=5.5..20v; i=10ma 5.1.7 gate drive output voltage tj=-40c tj=25c tj=150c v g_5 ?? 1.4 1.2 1.0 v uvlo; vs<=5.5v 5.1.8 gate drive output voltage high side tj=-40c tj=25c tj=150c v g_hs ?? 1.4 1.2 1.0 vovervoltage 5.1.9 gate drive output voltage low side v g_ls ??0.2vovervoltage 5.1.10 low level input voltage of ixx, enax v i_ll ??1.0v? 5.1.11 high level input voltage of ixx, enax v i_hl 2.0??v? 5.1.12 low level input voltage of inh v i_ll ??0.75v? 5.1.13 high level input voltage of inh v i_hl 2.1??v? 5.1.14 input hysteresis of ihx, ilx, enax dv i 50 ? ? mv vs=5.5..8v 5.1.15 input hysteresis of ihx, ilx, enax dv i 100 200 ?- mv vs=8..20v 5.1.16 output bias current shx i shx 0.3 1.0 1.6 ma vshx=0..(vs+1); ilx=low; ihx=high 5.1.17 output bias current slx i slx 0.3 1.0 1.6 ma vslx=0..7v; ilx=low; ihx=high
TLE7183F description and electrical characteristics data sheet 14 v2.1, 2008-04-30 electrical characteristics mosfet drivers - dynamic characteristics v s = 5.5 to 20v, t j = -40 to +150 c, f pwm < 25khz , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.1.18 min. internal dead time t dt_min 50 ? 200 ns dt pin to gnd (r dt =0 ?) 5.1.19 programmable internal dead time t dt 0.26 0.64 1.07 2.02 0.41 1.05 1.85 3.82 0.56 1.45 2.63 5.62 s r dt =10 k ? r dt =47 k ? r dt =100 k ? r dt =1000 k ? 5.1.20 max. internal dead time t dt_max 2.33 ? 6.35 s dt pin open 5.1.21 turn on current, peak i g(on) ? 0.8 ? a vgxx-vsxx=0v; vs=5.5..8v; c=22nf; r load =1 ? 5.1.22 turn on current, peak i g(on) ? 1.5 ? a vgxx-vsxx=0v; vs=8..20v c=22nf; r load =1 ? 5.1.23 turn off current, peak i g(off) ? 1.5 ? a vgxx-vsxx=10v; vs=8..20v c=22nf; r load =1 ? 5.1.24 rise time (20-80%) t j = -40c t j = 25c t j = 150c t g_rise ? 150 400 400 700 ns c=22nf; r load =1 ? 5.1.25 fall time (20-80%) t j = -40c t j = 25c t j = 150c t g_fall ? 150 230 230 500 ns c=22nf; r load =1 ? 5.1.26 input propagation time (low on) t p(iln) 90 190 290 ns c=22nf; r load =1 ? 5.1.27 input propagation time (low off) t p(ilf) 0 100 200 ns c=22nf; r load =1 ? 5.1.28 input propagation time (high on) t p(ihn) 90 190 290 ns c=22nf; r load =1 ? 5.1.29 input propagation time (high off) t p(ihf) 0 100 200 ns c=22nf; r load =1 ? 5.1.30 absolute input propagation time difference (all channels turn on) t p(an) ??70nsc=22nf; r load =1 ? 5.1.31 absolute input propagation time difference (all channels turn off) t p(af) ??50nsc=22nf; r load =1 ? 5.1.32 absolute input propagation time difference (1channel high off - low on) t p(1hfln) ? ? 150 ns c=22nf; r load =1 ? 5.1.33 absolute input propagation time difference (1channel low off - high on) t p(1lfhn) ? ? 150 ns c=22nf; r load =1 ?
data sheet 15 v2.1, 2008-04-30 TLE7183F description and electrical characteristics 5.1.34 absolute input propagation time difference (all channel high off - low on) t p(ahfln) ? ? 150 ns c=22nf; r load =1 ? 5.1.35 absolute input propagation time difference (all channel low off - high on) t p(alfhn) ? ? 150 ns c=22nf; r load =1 ? 5.1.36 wake up time; inh low to high t inh_pen ? ? 20 ms driver fully functional; vs=6.5...8v; enax=low; cpx=cbx=4.7f 5.1.37 wake up time; inh low to high t inh_pen ? ? 10 ms driver fully functional; vs=8..20v; enax=low; cpx=cbx=4.7f; 5.1.38 wake up time logic functions; inh low to high t inh_log ? ? 10 ms diagnostic, opamp working; vs=6.5...8v; enax=low; cpx=cbx=4.7f 5.1.39 wake up time logic functions; inh low to high t inh_log ??5msdiagnostic, opamp working; vs=8..20v; enax=low; cpx=cbx=4.7f 5.1.40 inh propagation time to disable the output stages t inh_p(o) ? ? 10 s vs=5.5..8v 5.1.41 inh propagation time to disable the output stages t inh_p(o) ??8svs=8..20v 5.1.42 inh propagation time to disable the entire driver ic t inh_p(ic) ??300s? 5.1.43 supply voltage v s for wake up v vswu 6.5 ? ? v diagnostic, opamp working; 5.1.44 charge pump frequency f cp 38 55 72 khz ? electrical characteristics mosfet drivers - dynamic characteristics v s = 5.5 to 20v, t j = -40 to +150 c, f pwm < 25khz , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
TLE7183F data sheet 16 v2.1, 2008-04-30 5.2 protection and diagnostic functions 5.2.1 short circuit protection the TLE7183F provides a short circuit protection for the external mosfets. it is a monitoring of the drain-source voltage of the external mosfets. as soon as this voltage is higher than the short circuit detection limit, a timer will start to run. the short circuit detection level is programmed fix in the chip. 5 different short circuit level options are available: table 2 short circuit detection level options after a delay of about 6 s all external mosfets will be switched off until the driver is reset by the enax pin. the error flag is set. the drain-source voltage monitoring of the short circuit detection for a certain external mosfet is active as soon as the corresponding input is set to "on" and the dead time is expired. 5.2.2 overcurrent warning the TLE7183F offers the possibility to shut down the output stages if a current threshold is reached. (see figure 4 ). the output of the current sense opamp is connected to an integrated comparator, comparing the amplified current sense signal with an external adjustable threshold value. after the comparator a blanking time (1.5 s typ.) is implemented to avoid false triggering caused by overswing of the current sense signal. if the overcurrent situation is detected, only an error signal is given. during overcurrent the driver ic works normally. the error signal disappears as soon as the current decreases below the overcurrent limit set on the vthoc pin. the error signal disappears as well when the current commutates from the low side mosfet to the associated high side mosfet (no current through the shunt resistor). it is the decision of the user to react on the over current signal by modifying the ixx patterns to lower the current. 5.2.3 dead time and shoot through protection in bridge applications it has to be assured that the external high side and low side mosfet are not "on" at the same time, connecting directly the battery voltage to gnd. the dead time generated in the TLE7183F is fixed to a minimum value of 50..200ns if the dt pin is connected to gnd. this function assures a minimum dead time if the input signals coming from the c are faulty. the dead time can be increased beyond the internal fixed dead time by connecting the dt pin via a dead time resistor r dt to gnd - the larger the dead time resistor the larger the dead time (for details pls. see the ?dynamic characteristic? table in the mosfet driver section). the exact dead time of the bridge is usually controlled by the pwm generation unit of the c. in addition to this dead time, the TLE7183F provides a locking mechanism, avoiding that both external mosfets of one half bridge can be switched on at the same time. this functionality is called shoot through protection. if the command to switch on both high and low side switches in the same half bridge is given at the input pins, the command will be ignored. tle7183 typ. short ciruit detection level scd1 0.5v scd2 0.75v scd3 1.0v scd4 1.5v scd5 2.0v
data sheet 17 v2.1, 2008-04-30 TLE7183F 5.2.4 undervoltage shut down the TLE7183F has an integrated undervoltage shut down, to assure that the behavior of the device is predictable in all supply voltage ranges. if the voltage of a charge pump buffer capacitors cbx reaches the undervoltage shut down level for a minimum specified filter time, the gate-source voltage of all external mosfets will be actively pulled to low. in this situation the short circuit detection of this output stage is deactivated to avoid a latching shut down of the driver. as soon as the charge pump buffer voltage recovers, the output stage condition will be aligned to the input patterns automatically. this allows to continue operation of the motor in case of undervoltage shut down without a reset by the c. undervoltage shut down will not occur when v s > 6 v, q g < 250 nc, f pwm < 25 khz, and the charge pump capacitors cxx = 4.7 f. 5.2.5 overvoltage shut down the TLE7183F has an integrated overvoltage shut down to avoid destruction of the ic at high supply voltages. the voltage is observed at the vs and the vdh pin. when one of them or all of them exceed the overvoltage shut down level for more than the specified filter time then the external mosfets are switched off. in addition, overvoltage will shut down the charge pumps and will discharge the charge pump capacitors. this results in an undervoltage condition which will be indicated on the errx pins. during overvoltage shut down the external mosfets and the charge pumps remain off until a reset is performed. 5.2.6 overtemperature warning if the junction temperature is exceeding typ. 170c an error signal is given as warning. the driver ic will continue to operate in order not to disturb the application. the warning is removed automatically when the junction te mperature is cooling down.it is in the responsibility of the user to protect the device against overtemperature destruction. 5.2.7 err pins the TLE7183F has two status pins to provide diagnostic feedback to the c. the outputs of these pins are 5v push pull stages, they are either high or low. table 3 overview of error conditions table 4 behaviour at different error conditions note: all errors do not lead to sleep mode. sleep mode is only initiated with the inh pin. the latch and restart behaviour allows to distinguish between the different error types combined at the err signals. err1 err2 driver conditions low low no errors high low overtemperature or overvoltage high high undervoltage low high short circuit detection or overcurrent error condition restart behavior shuts down... short circuit detection latch, reset must be performed at enax pin all external power -mosfets overcurrent warning self clearing nothing undervoltage auto restart all external power -mosfets overvoltage latch, reset must be performed at enax pin all external power -mosfets overtemperature warning self clearing nothing
TLE7183F data sheet 18 v2.1, 2008-04-30 table 5 priorisation of errors reset of error registers and disable the TLE7183F can be reseted by the enable pins enax. if one or two enax pins is pulled to low for a specified minimum time, the error registers are cleared and the external mosfets are switched off actively. during disable only the errors undervoltage shut down and overtemperature warning are shown. other errors are not displayed. 5.2.8 electrical characteristics priority error 1 short circuit detection 2 undervoltage detection 3 overvoltage detection 4 overtemperature overcurrent electrical characteristics - protection and diagnostic functions v s = 5.5 to 20v, t j = -40 to +150 c , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. overtemperature 5.2.1 overtemperature warning t j(ow) 150 170 190 c ? 5.2.2 hysteresis for overtemperature warning dt j(ow) ?20?c? overcurrent warning 5.2.3 overcurrent threshold v thoc 2 ? 4.5 v vs=5.5..8v 5.2.4 overcurrent threshold v thoc 2?4.8vvs=8..20v 5.2.5 input offset voltage of oc comp v ocof -50 ? 50 mv ? 5.2.6 input offset voltage temperature drift of oc comp 1) v io -5?5mv? 5.2.7 over current protection threshold hysteresis dv thoc 25 ? mv vs=5.5..8v 5.2.8 over current protection threshold hysteresis dv thoc 50 80 ? mv vs=8..20v 5.2.9 filter time of over current protection t oc 1.0 1.5 3.0 s short circuit protection 5.2.10 filter time of short circuit protection t scp(off) 4.5 6.8 9 s default 5.2.11 maximum duty cycle for no scd 2) d yscdmax ??6%fpwm=20khz at ihx or ilx and at static applied sc 5.2.12 minimum duty cycle for periodic scd 2) d yscdmin 13 ? ? % fpwm=20khz at ihx or ilx and at static applied sc
data sheet 19 v2.1, 2008-04-30 TLE7183F 5.2.13 short circuit protection detection level scd1 v scp1(off) 0.3 0.5 0.65 v 5.2.14 short circuit protection detection level scd2 v scp2(off) 0.6 0.75 0.9 v 5.2.15 short circuit protection detection level scd3 v scp3(off) 0.85 1.0 1.15 v 5.2.16 short circuit protection detection level scd4 v scp4(off) 1.35 1.5 1.65 v 5.2.17 short circuit protection detection level scd5 v scp5(off) 1.8 2.0 2.2 v err pins 5.2.18 high level output voltage of errx v oherr 4.0 ? 5.2 v i= -0.2ma 5.2.19 low level output voltage of errx v olerr -0.1 ? 0.4 v i= 0.2ma 5.2.20 propagation time difference err1 to err2 t pd(err) ? 200 ns ? 5.2.21 rise time errx (20 - 80 %) t r(err) 50 ? 600 ns c load =100pf 5.2.22 fall time errx (80 - 20 %) t f(err) 50 ? 400 ns c load =100pf over- and undervoltage 5.2.23 overvoltage shut down v ov(off) 28 ? 33 v on vs and/or vdh 5.2.24 overvoltage filter time t ov 30 ? 65 s ? 5.2.25 undervoltage shut down cb1 v uv1 6.75 ? 8.25 v cb1 to gnd 5.2.26 undervoltage shut down cb2 v uv2 3.9 ? 5.7 v cb2 to vdh 5.2.27 undervoltage shut down hysteresis of cb1 and cb2 v duv ?1.0?v? 5.2.28 undervoltage filter time t uv 1?3s? reset and enable 5.2.29 reset time to clear err registers t res1 2.0??s? 5.2.30 low time of enax signal without reset t res0 ??0.5s? 5.2.31 enax propagation time (high --> low) t pena_h-l ??2.0s? 5.2.32 enax propagation time (low --> high) t pena_l-h ??0.5s? 5.2.33 return time to normal operation at auto-restart t ar ??1.0s? 1) not subject to production test; specified by design 2) parameters describe the behaviour of the internal scd circuit. therefore only internal delay times are considered. in application dead-/ delay times determined by application circuit (switching times of mosfets, adjusted dead time) have to be considered as well. electrical characteristics - protection and diagnostic functions (cont?d) v s = 5.5 to 20v, t j = -40 to +150 c , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
TLE7183F data sheet 20 v2.1, 2008-04-30 5.3 shunt signal conditioning the TLE7183F incorporates a fast and precise operational amplifier for conditioning and amplification of the current sense shunt signal. additionally, one reference bias buffer is integrated to provide an adjustable bias reference for the three opamps. the voltage devider on the vri pin should be less than 50 kohm, the filtering capacitor less than 1.2 f - if needed at all. the gain of the opamp is adjustable by external resistors within a range of 5 to 15. when v(isp) = v(isn), vo provides the reference voltage vro. vro is normally half of the regulated voltage provided from an external voltage regulator for the adc used to read the current sense signal. the additional buffer allows bi-directional current sensing and permits the adaptation of the reference bias to different c i/o voltages. the reference buffer assures a stable reference voltage even in the high frequency range. the output of the i-dc link opamp vo is not short-circuit proof. figure 4 shunt signal conditioning block diagram and over current limitation over current warning see chapter 5.2.2 .
data sheet 21 v2.1, 2008-04-30 TLE7183F 5.3.1 electrical characteristics electrical characteristics - current sense signal conditioning v s = 5.5 to 20v, t j = -40 to +150 c, f pwm < 25khz , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.3.1 series resistors r s 100 500 1000 ? ? 5.3.2 feedback resistor limited by the output voltage dynamic range r fb 2000 7500 ? ? ? 5.3.3 resistor ratio (gain ratio) r fb / r s 5?15?? 5.3.4 steady state differential input voltage range across vin 1) v in(ss) -400 ? 400 mv ? 5.3.5 transient differential input voltage range across vin v in(tr) -800 ? 800 mv ? 5.3.6 input differential voltage (isp - isn) v idr -800 ? 800 mv ? 5.3.7 input voltage (both inputs - gnd) (isp - gnd) or (isn -gnd) v ll -800 ? 1500 mv vs=5.5..8v 5.3.8 input voltage (both inputs - gnd) (isp - gnd) or (isn -gnd) v ll -800 ? 2000 mv vs=8..20v 5.3.9 input offset voltage of the i-dc link opamp v io ?1+/-5mvr s =500 ? ; v cm =0v; v o =1.65v; v ri =1.65v 5.3.10 input offset voltage temperature drift of the i-dc link opamp 2) v io ?12mvr s =500 ? ; v cm =0v; v o =1.65v; v ri =1.65v 5.3.11 input offset voltage of the reference buffer v io 1+/-5mv? 5.3.12 input offset voltage temperature drift of the reference buffer 2) v io 12mv? 5.3.13 input range at vri v io 1.2 ? 2.8 v ? 5.3.14 input bias current (isx to gnd) i ib ??300av cm =0v; v o =open 5.3.15 high level output voltage of vo v oh 4.8 ? 5.2 v v ri =1.65v/2.5v; i oh =-3ma 5.3.16 low level output voltage of vo v ol -0.1 ? 0.2 v v ri =1.65v/2.5v; i oh =3ma 5.3.17 output voltage of vo 3) v ri = 2.5v, v ri =1.65v v or 2.42 1.58 2.50 1.65 2.58 1.73 vv in(ss) =0v; gain=15; 5.3.18 temperature drift of output voltage of vo 3) v o 0?32mvv in(ss) =0v; gain=15 5.3.19 output short circuit current i sc 5??ma? 5.3.20 differential input resistance 2) r i 100??k ? ? 5.3.21 common mode input capacitance 2) c cm ??10pf10khz
TLE7183F data sheet 22 v2.1, 2008-04-30 5.3.22 common mode rejection ratio at dc cmrr = 20*log((vout_diff/vin_diff) * (vin_cm/vout_cm)) cmrr 80 100 ? db ? 5.3.23 common mode suppression 4) with cms = 20*log(vout_cm/vin_cm) freq =100khz freq = 1mhz freq = 10mhz cms ? 62 43 33 ? db vin=360mv* sin(2* *freq*t); rs=500 ? ; rfb=7500 ? ; vri=1.65/2.5v 5.3.24 slew rate dv/dt 310?v/sgain>= 5; r l =1.0k ? ; c l =500pf 5.3.25 large signal open loop voltage gain (dc) a ol 80 100 ? db ? 5.3.26 unity gain bandwidth gbw 10 20 ? mhz r l =1k ? ; c l =100pf 5.3.27 phase margin 2) m ? 50 ? gain>= 5; r l =1k ? ; c l =100pf 5.3.28 gain margin 2) a m ?12?dbr l =1k ? ; c l =100pf 5.3.29 bandwidth bw g 1.6 ? ? mhz gain=15; r l =1k ? ; c l =500pf; r s =500 ? 5.3.30 output settle time to 98% 1) t set ?11.8sgain=15; r l =1k ? ; c l =500pf; 0.3 data sheet 23 v2.1, 2008-04-30 tle183f 5.4 phase voltage feedback the TLE7183F incorporates an fast conversion of the phase voltages into logic signals. the threshold values are proportional to v dh . the outputs are 5v push pull stages. when they are not used they can be left open. figure 5 block diagram phase voltage feedback 5.4.1 electrical characteristics electrical characteristics - phase voltage feedback v s = 5.5 to 20v, t j = -40 to +150 c, f pwm < 25khz , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.4.1 low level threshold v ilfb 35 40 45 % of vdh vdh>5.5v v shx decreasing 5.4.2 high level threshold v ihfb 55 60 65 % of vdh vdh>5.5v v shx decreasing 5.4.3 high level output voltage of x_fb v ohfb 4.0 5.2 v i= -0.5ma 5.4.4 low level output voltage of x_f v olfb -0.1 0.2 v i= 0.5ma 5.4.5 propagation delay time incl. rise or fall time t pdfb 110 ns c load <100pf 5.4.6 matching of propagation delay time t dpdfb 30 ns
TLE7183F application description data sheet 24 v2.1, 2008-04-30 6 application description in the automotive sector there are more and more applications requiring high performance motor drives, such as electro-hydraulic or electric power steering. in these applications 3 phase motors, synchronous and asynchronous, are used, combining high output performance, low space requirements and high reliability. figure 6 application circuit - tle 7183 f note: this is a very simplified example of an application circuit. the function must be verified in the real application. sh1 v bat =12v c or digital asic gh1 sh2 gh2 gl1 gl2 vs il1 ih1 c vs 4.7f r vs 10 ? gnd sl1 sh3 gh3 sl2 gl3 sl3 il2 ih2 il3 ih3 gnd vdh tle 7183 f p-gnd err1 err2 ch1 cl1 c cp1 4.7f cb1 c cb1 4.7f ch2 cl2 c cp2 4.7f cb2 c cb2 4.7f vro isp isn vri vthoc vo shunt r s r s r fb r fb v_fb w_fb u_fb 5v 5v adc inh ena2 dt r dt agnd tp ena1 to sub c or asic r vdh r g r g r g r g r g r g c b 1000f c b 1000f c b 1000f c c 1f c c 1f c c 1f
data sheet 25 v2.1, 2008-04-30 TLE7183F application description 6.1 layout guide lines please refer also to the simplified application example. ? three seperated bulk capacitors c b should be used - one per half bridge ? three seperated ceramic capacitors c c should be used - one per half bridge ? each of the 3 bulk capacitors c b and each of the 3 ceramic capacitors c c should be assigned to one of the half bridges and should be placed very close to it ? the components within one half bridge should be placed close to each other: high side mosfet, low side mosfet, bulk capacitor c b and ceramic capacitor c c (c b and c c are in parallel) and the shunt resistor form a loop that should be as small and tight as possible. the traces should be short and wide ? the three half bridges can be seperated; yet, when there is one common gnd referenced shunt resistor for the three half bridges the sources of the three low side mosfets should be close to each other and close to the common shunt resistor ? vdh is the sense pin used for short circuit detection; vdh should be routed (via rvdh) to the common point of the drains of the high side mosfets to sense the voltage present on drain high side ? cb2 is the buffer capacitor of charge pump 2; its negative terminal should be routed to the common point of the drains of the high side mosfets as well - this connection should be low inductive / resistive ? additional r-c snubber circuits (r and c in series) can be placed to attenuate/suppress oscillations during switching of the mosfets, there may be one or two snubber circuits per half bridge, r (several ohm) and c (several nf) must be low inductive in terms of routing and packaging (ceramic capacitors) ? the exposed pad on the backside of the vqfn should be connected to gnd 6.2 further application information ? for further information you may contact http://www.infineon.com/
TLE7183F revision history data sheet 26 v2.1, 2008-04-30 7 revision history version date changes v2.1 2007-08-08 chapter 1 : title overview added chapter 1 : description paragaph 2 added chapter 1 : edit table overview chapter 4.1 : parameter 4.1.26 ambient temperature deleted chapter 5.2.1 : table 2: short circuit detection level options added chapter 5.2.8 : parameter 5.2.13-5.2.17 min. max values defined; comment on request deleted v2.0 2006-10-18 change of specified supply voltage range from vs=8..20v to vs=5.5..20v incl. adjustment of values final datasheet
data sheet 27 v2.1, 2008-04-30 TLE7183F package outlines 8 package outlines figure 7 vqfn 48 package green product to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gvq0104 9 a index marking b 0.9 max. 0.08 48x 1 2 m a x . s e a t i n g p l a n e c (0.2) 0.05 max. standoff 1 12 37 48 13 24 25 36 1 1 x 0 . 6 5 = 7 . 1 5 0 . 6 5 11 x 0.65 = 7.15 0.65 6 . 8 0 . 1 5 0.05 0.35 0.1 9 0.1 8.75 0.1 48x a m b c 0.15 6.8 index marking 0.05 0.55 (0.65) 0 . 1 9 0 . 1 8 . 7 5 gps09181 you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
edition 2008-04-30 published by infineon technologies ag 81726 munich, germany ? 2008 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.


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